1. FIELD OF THE INVENTION
The present invention relates to a testing system for testing integrated circuits.
2. DESCRIPTION OF RELATED ART
After fabrication, integrated circuits are typically tested to detect defects in the circuits. The circuits are typically inserted into a test system which sends and receives a number of test signals in accordance with a series of test specifications. High speed integrated circuits that are designed to drive a number of devices typically have a relative low output impedance. The chip impedance is frequently much smaller than the impedance of the testing system, creating a impedance mismatch between the two members. The impedance mismatch can cause "ringing" when the digital signals being transmitted change from a high state to a low state, or from a low state to a high state.
Prior attempts to reduce or eliminate signal ringing in a test apparatus include adding a resistor between the chip and the testing system. Adding a resistor dampens the ringing of the signal, but may also introduce undesirable propagation delays in the signal transitions. Additionally, the resistor can reduce the voltage levels of the digital signals. Producing voltage drops in the input/output (I/O) signals is generally undesirable, particularly for high speed chips which typically have low voltage swings.
Another method for dampening signal ringing is to install clamping diodes in the testing system that clamp voltages greater than a predetermined value. To effectively use clamping diodes, the ground noise must be kept to a minimum. Neutralizing the ground noise typically requires the inclusion of additional grounding pins. Because most integrated circuit packages have a fixed pin count, increasing the ground pins would result in a corresponding decrease in the I/O pins of the circuit. Additionally, it is impractical to place clamping diodes on the circuit to control ringing when the testing system is driving the chip. It is therefore desirable to have a testing device which can dampen signal ringing, without increasing the number of pins in the integrated circuit, or introducing excessive voltage drops and propagation delays in the signals.